Strategic Objectives
• Discover the architectural secrets of skipping zero-valued multiplications.
• Understand the mechanics of real-time zero-detection logic.
• Master high-efficiency data encoding for compressed neural streams.
• Learn to design hardware that thrives on network sparsity.
The Core Challenge
Traditional processors waste massive energy and time calculating zero-valued operations that don't change the final output of neural networks.
01
The Essence of Sparsity
02
Foundations of AI Hardware
03
The Cost of a Zero
04
Activation Sparsity
05
Weight Sparsity
06
Logic Gates for Detection
07
Clock Gating Strategies
08
Data Compression Formats
09
The Multiply-Accumulate Barrier
10
Zero-Value Prediction
11
Memory Access Patterns
12
Hardware Schedulers
13
Bit-Serial Processing
14
Parallelism and Sparsity
15
Quantization Effects
16
Systolic Array Innovations
17
The Dark Silicon Problem
18
Benchmarking Efficiency
19
Compiler Support
20
In-Memory Computing
21