Strategic Objectives
• Understand the physics of hole trapping and interface state generation.
• Master layout techniques like Enclosed Layout Transistors (ELT) to mitigate leakage.
• Learn to predict long-term device life cycles in high-radiation orbits.
• Implement robust circuit-level strategies to compensate for parameter shifts.
The Core Challenge
Total Ionizing Dose (TID) causes cumulative, permanent degradation in CMOS oxides, shifting threshold voltages until mission-critical systems fail.
01
Foundations of Radiation Environments
02
The Physics of TID
03
CMOS Architecture Basics
04
Hole Trapping and Transport
05
Threshold Voltage Instability
06
Interface State Generation
07
Leakage Current Pathways
08
Annealing and Recovery
09
The ELARD Phenomenon
10
Hardening by Process
11
Hardening by Design (HBD)
12
Isolation Technologies
13
SOI vs. Bulk CMOS
14
Analog and Mixed-Signal Challenges
15
Memory Systems and TID
16
Dosimetry and Measurement
17
Testing Standards
18
Modeling and Simulation
19
The Van Allen Belts
20
Deep Space and Nuclear Applications
21
The Future of Hardened CMOS
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