Strategic Objectives
• Master the architecture of high-bandwidth Network-on-Chip (NoC) designs.
• Optimize data flow to eliminate latency in large-scale tensor operations.
• Explore advanced routing algorithms tailored for neural workloads.
• Bridge the gap between raw compute power and real-world throughput.
The Core Challenge
As NPU compute power scales, the inability to move massive tensors efficiently creates a communication bottleneck that leaves processing elements idle.
01
The Evolution of NPUs
02
The Interconnect Imperative
03
NoC Fundamentals
04
Topological Design
05
Tensor Data Movement
06
Routing Algorithms
07
Flow Control Mechanisms
08
Switching Strategies
09
Router Microarchitecture
10
Arbitration and Allocation
11
Memory Hierarchies in NPUs
12
Bandwidth Optimization
13
Latency Mitigation
14
Energy-Efficient Interconnects
15
Synchronization and Coherency
16
Quality of Service (QoS)
17
Fault Tolerance and Reliability
18
3D Integration and TSVs
19
Photonic Interconnects
20
Modeling and Simulation
21