Strategic Objectives
• Harness Scala’s functional power to automate complex digital architectures.
• Build highly parameterized hardware generators that scale effortlessly.
• Bridge the gap between software-level abstraction and silicon-level precision.
• Streamline verification and testing using modern software engineering paradigms.
The Core Challenge
Traditional RTL design is plagued by verbosity, lack of reusability, and the rigid constraints of procedural Verilog.
01
The Paradigm Shift
02
The Scala Foundation
03
Functional Programming for Silicon
04
Chisel Basics
05
Object-Oriented Hardware
06
Advanced Parameterization
07
The FIRRTL Intermediate Representation
08
Combinational Circuits
09
Sequential Logic Mastery
10
Finite State Machines
11
The Power of Bundles and Vecs
12
Memory Systems
13
Arithmetic and Data Paths
14
Verification and Testing
15
The RISC-V Connection
16
TileLink and Interconnects
17
Diplomacy and Parameter Negotiation
18
Digital Signal Processing in Chisel
19
FPGA Prototyping
20
The ASIC Flow
21