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Volume

The Transceiver Blueprint

Mastering Silicon-Level Transceiver Design for Next-Gen EW Hardware

Shrink the system, not the performance.

Strategic Objectives

• Master high-frequency transceiver architectures on CMOS and SiGe.

• Optimize power efficiency for high-density hardware environments.

• Overcome the physical limitations of on-chip passive components.

• Integrate complex mixers and amplifiers into a single silicon die.

The Core Challenge

Traditional RF design fails when faced with the brutal constraints of modern electronic warfare and silicon-level miniaturization.

01

Foundations of RFIC

02

Semiconductor Fabrications

03

Transceiver Architectures

04

The Low Noise Amplifier

05

Frequency Up-conversion

06

Voltage-Controlled Oscillators

07

Phase-Locked Loops

08

Integrated Power Amplifiers

09

On-Chip Passive Components

10

Impedance Matching Networks

11

Noise Figure and Distortion

12

Direct Conversion Challenges

13

Intermediate Frequency Stages

14

Integrated Antennas

15

Isolation and Crosstalk

16

Silicon Thermal Management

17

Packaging for RF

18

ESD Protection for RFICs

19

Mixed-Signal Integration

20

Testing and Characterization

21

Future Trends in EW Silicon

Available eBook Editions