Strategic Objectives
• Understand the core architecture of minimalist RTOS kernels.
• Optimize memory footprints for microcontrollers with limited SRAM.
• Master deterministic scheduling and interrupt handling techniques.
• Implement advanced power management for long-term edge deployment.
The Core Challenge
Edge devices are shrinking, but the demand for reliability and real-time response is exploding, leaving developers struggling with overhead.
01
The Essence of Embedded OS
02
The Real-Time Imperative
03
Microkernel Architecture
04
Context Switching Mechanics
05
Priority-Based Scheduling
06
Interrupt Service Routines
07
Memory Management Units
08
Static vs. Dynamic Allocation
09
Inter-Process Communication
10
Synchronization Primitives
11
Priority Inversion Solutions
12
Clock Cycles and Timers
13
Power-Aware Design
14
Reentrancy and Thread Safety
15
Device Driver Models
16
Bootloaders and Initialization
17
Error Handling and Watchdogs
18
The HAL Layer
19
Binary Footprint Optimization
20
Direct Memory Access
21