Strategic Objectives
• Eliminate energy-intensive data movement by computing directly within DRAM and SRAM.
• Unlock massive parallel throughput for deep learning and real-time analytics.
• Understand the architectural shift from CPU-centric to memory-centric design.
• Master the hardware-software co-design required for the next era of silicon.
The Core Challenge
For decades, the Von Neumann architecture has forced a costly data migration between memory and CPU, resulting in the 'memory wall' that stifles AI and Big Data performance.
01
The Von Neumann Bottleneck
02
Defining Processing-In-Memory
03
The Physics of DRAM
04
SRAM-Based Computation
05
The Memory Wall Crisis
06
Emerging Non-Volatile Memory
07
Analog Computing in Memory
08
3D-Stacked Architectures
09
Logic-In-Memory Design
10
Energy-Efficient Computing
11
Parallelism Redefined
12
Accelerating Deep Learning
13
The Role of Memristors
14
Programming for PIM
15
Compilers and Toolchains
16
Data Locality and Movement
17
Security and Privacy
18
Heterogeneous Integration
19
The Economics of Silicon
20
Industry Use Cases
21
The Future of Post-Moore Computing
Explore Research Ecosystem
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